Chapter 10: Connecting to Armv8-R AArch64 PEs

This chapter describes the requirements for connecting a GIC to PEs that implement Armv8-R AArch64: • Armv8-R AArch64 CPU interface requirements .

Collectively, these restrictions are referred to as GICv3.2.

10.1 Armv8-R AArch64 CPU interface requirements

10.1.1 Impact to legacy mode

Legacy operation is not supported. When GIC is used with Armv8-R AArch64 PEs, the ICC_SRE_ELx.SRE bits are RES1.

10.1.2 GICv3.1 extended INTID range support

When GIC v3.1 is used with Armv8-R AArch64 PEs, ICC_CTLR_EL1.ExtRange==0 is deprecated.

Note Arm recommends that Armv8-R AArch64 PEs report ICC_CTLR_EL1.ExtRange==1, indicating that the GICv3.1 extended SPI and PPI ranges are supported.

10.1.3 LPI support

Armv8-R AArch64 PEs support LPIs.

GIC IRIs that support LPIs can be connected to PEs that implement Armv8-R AArch64.

10.1.4 Local SError generation support

Armv8-R AArch64 does not support local SError generation by the CPU interface. When GIC is used with Armv8-R AArch64 PEs, the ICH_VTR_EL2.SEIS and ICC_CTLR_EL1.SEIS are RES0.

10.1.5 Virtualization support

When GIC is used with Armv8-R AArch64 PEs, the ICH_VTR_EL2.TDS is RES1, indicating that ICH_HCR_EL2.TDIR is supported.